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參數資料
| 型號： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網擴頻PC卡參考設計中的應用？欺詐郵件（PDF格式） |
| 文件頁數： | 8/25頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 20575 |
7
Table 1. Am79C930 Pin Connections
AMD
Am79C930
Pin Name
ACT
Pin
No.
98
I/O
O
AMD Am79C930 Pin
Function
LED output, controlled by
firmware
GND
LED output, controlled by
firmware
802.11 HARRIS DS PHY PC
CARD System Connections
Yellow LED
I/O
802.11 HARRIS DS
PHY PC CARD
System Function
Indicates currrent RX
or TX activity
VSST
LNK
99
100
I
O
GND
Green LED
I
Indicates a current
association with a
BSS
Synthesizer serial bus
clock input
Control register serial
bus clock input
SDCLK
101
O
Note that this pin is
shared by both serial
busses (i.e., synthesizer
chip serial bus and
baseband chip serial
bus)
Note that this pin is
shared by both serial
busses (i.e., synthesizer
chip serial bus and
baseband chip serial
bus)
API will determine signal
timing
3.5-V supply
HFA3524.SYNTH_CLK (Pin
11)
HSP3824.SCLK
I
I
SDDATA
102
I/O
HFA3524.SYNTH_DATA (Pin
12)
HSP3824.SDATA (Pin 25)
I
Synthesizer serial bus
data pin
Control register serial
bus clock input
I/O
SDSEL3
103
O
HSP3824.RW (Pin 8)
I
Control register serial
bus read-write select
VDDT
104,
125
105
I
3.5-V supply
SDSEL2
O
API will determine signal
timing
HSP3824.AS (Pin 23)
I
Selects between
address and data
registers in the
HSP3824
Selects the HSP3824
device for register
access
SDSEL1
107
O
API will determine signal
timing
HSP3824.CS (Pin 9)
I
SAR[6:0]
TXC
O
I
A/D converter output
TX clock - controls
delivery of TXDATA
Buffered clock output
Enables LFCLK
NC
HSP3824.TXCLK (Pin 4)
115
O
TX clock - controls
delivery of TXDATA
LFCLK
LFPE
117
118
O
O
NC
HSP3824.RESET (Pin 28)
I
Reset input for
HSP3824 device
HFCLK
HFPE
TXDATA
RXPE
119
120
121
122
O
O
O
O
Buffered clock output
Enables HFCLK
TX output data
API will create timing
NC
NC
HSP3824.TXD (Pin 3)
HSP3824.RX_PE (Pin 33)
I
I
TX input data
Baseband processor
RX enable input.
RX output data
RX clock decoded
from channel activity
RXDATA
RXCIN
123
124
I
I
RX input data
RX clock input for
incoming RX frames
HSP3824.RXD (Pin 35)
HSP3824.RXCLK (Pin 36)
O
O
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