參數(shù)資料
型號(hào)： 211AI01L
英文描述： LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
中文描述： 低偏移，1至2差分至HSTL扇出緩沖器
文件頁(yè)數(shù)： 7/13頁(yè)
文件大小： 166K
代理商： 211AI01L
85211AMI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 1, 2005
7
Integrated
Circuit
Systems, Inc.
ICS85211I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts differential input signals of both V
and V
to meet the V
and V
input requirements.
Figures 3A
to 3D
show interface examples for the ICS85211I-01 clock input
driven by most common driver types. The input interfaces sug-
gested here are examples only. Please consult with the vendor
F
IGURE
3A. ICS85211I-01 CLK/
N
CLK I
NPUT
D
RIVEN
BY
H
I
P
ER
C
LOCK
S HSTL D
RIVER
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
of the driver components to confirm the driver termination require-
ment. For example in
Figure 3,
the input termination applies for
ICS HiPerClockS HSTL drivers. If you are using an HSTL driver
from another vendor, use their termination recommendation.
F
IGURE
3B. ICS85211I-01 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
(I
NTERFACE
1)
F
IGURE
3C. ICS85211I-01 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
(I
NTERFACE
2)
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
R2
84
Zo = 50 Ohm
3.3V
R4
LVPECL
R1
84
3.3V
F
IGURE
3D. ICS85211I-01 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
R3
125
LVPECL
R1
84
C1
R2
84
Input
CLK
nCLK
R5,R6 locate near the driver pin.
Zo = 50 Ohm
3.3V
3.3V
C2
R4
125
R6
100-200
Zo = 50 Ohm
R5
100-200
3.3V
R
ECOMMENDATIONS
FOR
U
NUSED
O
UTPUT
P
INS
O
UTPUTS
:
HSTL O
UTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
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