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參數(shù)資料
| 型號： | 2128VL |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | 2.5V的在系統(tǒng)可編程超快⑩高密度可編程邏輯器件 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 214K |
| 代理商： | 2128VL |
Specifications
ispLSI 2128VL
5
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-135
MIN.
—
—
135
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030/2128VL
1
3
2
1
( )
-100
MIN.
—
—
100
MAX.
7.5
10.0
MAX.
10.0
13.0
DESCRIPTION
#
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
ns
ns
MHz
—
—
—
—
—
A
—
4
5
6
7
8
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
—
—
—
4.5
—
—
—
—
5.0
MHz
MHz
ns
ns
ns
—
0.0
—
0.0
—
—
A
—
A
—
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay, ORP Bypass
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
6.0
—
0.0
—
5.5
—
—
—
—
—
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
—
0.0
—
—
6.5
—
—
—
—
—
—
—
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
3.5
3.5
—
—
—
—
ns
ns
95
143
5.0
—
5.5
—
8.0
—
12.0
12.0
7.0
7.0
77
100
6.5
8.0
5.0
5.0
13.5
15.0
15.0
9.0
9.0
-150
MIN. MAX.
—
—
150
6.0
8.5
—
—
—
—
4.0
—
—
0.0
5.0
—
0.0
—
5.0
—
—
—
—
3.0
3.0
—
—
111
166
4.0
—
5.0
—
6.0
—
10.0
10.0
6.0
6.0
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