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參數(shù)資料
| 型號： | 21823 |
| 英文描述： | 3.3V Spread-Spectrum EconOscillator |
| 中文描述： | ？lanSC300和？lanSC310微控制器內存管理 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 65K |
| 代理商： | 21823 |
4
élan
TM
SC300 and élanSC310 Microcontrollers Memory Management
The following should also be noted:
I
The 32-Kbyte Display SRAM region, B8000–
BFFFF, can revert to Local/ISA by disabling the
internal video controller, or it can be moved to
B0000–B7FFF by setting the internal video
controller to HGA mode.
I
When DRAM is enabled, the range A0000–FFFFF
is not automatically mapped to DRAM. Its mapping
remains at what it was before DRAM was enabled.
I
With 64-Kbyte granularity, blocks in regions A0000–
AFFFF and C0000–FFFFF can be mapped to
ROMCS.
I
With 16-Kbyte granularity, blocks in the region
C0000–FFFFF that are not already mapped to
ROMCS can be mapped to DRAM.
I
With 16-Kbyte granularity, the four blocks in the
range A0000–AFFFF and up to eight consecutive
blocks in the range C0000–F3FFF can be mapped
using MMSB and MMSA, which use translated
memory management. This translated memory
management allows each 16-Kbyte region to be
mapped to any 16-Kbyte boundary in any address
space except Local/ISA bus. This is discussed
further in the next section.
TRANSLATED MEMORY MANAGEMENT
When the élanSC300 microcontroller performs
translated memory management, it translates
addresses in addition to selecting the correct address
space for each access. A window in the CPU address
space is mapped to a particular target location in the
target address space.
The élanSC300 microcontroller implements translated
memory management via two MMS windows: MMSA
and MMSB. MMSA consists of eight consecutive
16-Kbyte regions starting at any 16-Kbyte boundary
from C0000–D4000. MMSB consists of four
consecutive 16-Kbyte regions starting at A0000. Each
16-Kbyte region can be mapped to any 16-Kbyte
boundary in any address space except Local/ISA bus.
This allows mapping to any address in DRAM,
ROMCS, or DOSCS. On the élanSC300
microcontroller only, you can also map to the four
PCMCIA memory spaces. Note that MMSA and MMSB
are the only means of accessing the four PCMCIA
memory spaces. They cannot be accessed via
non-translated memory management.
The particulars of programming MMSA and MMSB are
described in chapter 2 of the élanSC300
Microcontroller Programmer’s Reference Manual
,
order #18470. The following should be noted:
I
All of the 16-Kbyte pages in either MMSA or MMSB
can be enabled or disabled by a global switch for
each MMS system. In addition, each individual
16-Kbyte page within MMSA or MMSB can be
enabled or disabled. When a 16-Kbyte page is
disabled, addresses in that range map to whatever
they would map to with non-translated memory
management. For example, if MMSA starts at
C0000, and page 4 (D0000–D3FFF) is disabled,
then D0000–D3FFF will go to either Local/ISA bus,
ROMCS, or to DRAM using the rules discussed in
the previous section entitled Non-Translated
Memory Management.
A page can be enabled in MMSA or MMSB only if the
non-translated mapping for that page is Local/ISA bus.
A page cannot have a non-translated mapping to
DRAM or ROMCS space. For example, if F0000–
FFFFF is enabled for ROMCS mapping, and MMSA is
set to start at D4000, you cannot enable page 7 of
MMSA (F0000–F3FFF) because F0000–F3FFF is
already mapped to ROMCS. Note, however, that if
F0000–FFFFF is disabled for ROMCS mapping, you
could enable page 7 of MMSA and still have F4000–
FFFFF mapped to DRAM. This is possible because
DRAM mapping in this region can be enabled or
disabled on 16-Kbyte boundaries.
Translated Memory Management in
System Management Mode
System Management Mode (SMM) on the élanSC300
microcontroller involves the following mappings.
I
When SMM is entered via an SMI, CPU addresses
60000–63FFF map to a translated DRAM location
on a 16-Kbyte boundary. The system state is saved
at the bottom of this area before the SMI execution
starts. The address that 60000 maps to in DRAM
space is programmable using index registers A9h
and AAh. This region, sometimes called SMM RAM,
can thus be mapped to a DRAM location such as
AC000–AFFFF, which is normally unused because
AC000–AFFFF cannot be mapped to DRAM in
normal (non-SMM) system operation. This allows
SMM RAM to be invisible to normal system
operation.
I
Except for the region 60000–63FFF, the remainder
of the CPU address mappings is identical to what it
was before the SMI. Remember that the SMI
handler execution begins at FFFFF0 and that
FFFFF0 always maps to ROMCS (it is entirely
independent of the mapping of the 0F0000 block in
the lower 1 Mbyte). Also, remember that the
0F0000 block will not necessarily point to ROMCS
if it has been reprogrammed since processor reset.
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