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參數(shù)資料
| 型號(hào)： | 230Q1 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | CAN |
| 英文描述： | 3.3-V CAN TRANSCEIVERS |
| 中文描述： | 3.3 V的CAN收發(fā)器 |
| 文件頁(yè)數(shù)： | 8/30頁(yè) |
| 文件大?。?/td> | 488K |
| 代理商： | 230Q1 |
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SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS117C
–
JUNE 2001
–
REVISED JUNE 2002
8
www.ti.com
driver switching characteristics at T
A
= 25
°
C (unless otherwise noted)
SN65HVD232Q
PARAMETER
TEST CONDITIONS
MIN
TYP
35
70
35
50
55
MAX
UNIT
ns
ns
ns
ns
ns
tPLH
tPHL
tsk(p)
tr
tf
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|tP(HL)
–
tP(LH)|)
Differential output signal rise time
Differential output signal fall time
85
120
CL = 50 pF, See Figure 4
CL 50 F, See Figure 4
25
40
100
80
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
750
MAX
900
UNIT
mV
VIT+
VIT
–
Vhys
Positive-going input threshold voltage
See Table 1
Negative-going input threshold voltage
500
650
mV
Hysteresis voltage (VIT+
–
VIT
–
)
100
VOH
High-level output voltage
–
6 V
≤
VID
≤
500 mV, IO =
–
8 mA, See Figure 5
2.4
V
VOL
Low-level output voltage
900 mV
≤
VID
≤
6 V, IO = 8 mA, See Figure 5
VIH = 7 V
VIH = 7 V, VCC = 0 V
VIH =
–
2 V
VIH =
–
2 V, VCC = 0 V
Pin-to-ground,
VI = 0.4 sin(4E6
π
t) + 0.5 V
Pin-to-pin,
VI = 0.4 sin(4E6
π
t) + 0.5 V
Pin-to-pin, V(D) = 3 V
0.4
100
250
II
Other input at 0 V,
Other in ut at 0 V,
D = 3 V
100
350
μ
A
Bus input current
–
200
–
30
–
100
–
20
μ
A
Ci
CANH, CANL input capacitance
V(D) = 3 V,
32
pF
Cdiff
Differential input capacitance
V(D) = 3 V,
16
pF
Rdiff
RT
ICC
All typical values are at 25
°
C and with a 3.3-V supply.
Differential input resistance
40
70
100
k
k
CANH, CANL input resistance
Supply current
20
35
50
See driver
receiver switching characteristics at T
A
= 25
°
C (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
tsk(p)
tr
tf
t(loop)
t(loop)
t(loop)
Propagation delay time, low-to-high-level output
35
50
ns
Propagation delay time, high-to-low-level output
See Figure 6
35
50
ns
Pulse skew (|tP(HL)
–
tP(LH)|)
Output signal rise time
10
ns
See Figure 6
1.5
ns
Output signal fall time
1.5
ns
Total loop delay, driver input to receiver output
V(RS) = 0 V
RS with 10 k
to ground
RS with 100 k
to ground
70
135
Total loop delay, driver input to receiver output
Total loop delay, driver input to receiver output
105
535
175
920
ns
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