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參數(shù)資料
| 型號： | 23C256 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | CMOS 32Kx 8-Bit Mask ROM |
| 中文描述： | 的CMOS 32Kx 8位掩模ROM |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 242K |
| 代理商： | 23C256 |
A.C. test conditions
Output load: see figure right
Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (VCC=5V), 1.5V (VCC=3V)
Timing Diagrams
Propagation delay due to address (CE/CE/OE1/OE1 and OE/OE are active)
Propagation delay due to chip enable and output enable (address valid)
Functional Description
The HT23C256 has two modes, namely data
read mode and standby mode, controlled by
CE/CE/OE1/OE1 and OE/OE/NC inputs.
Standby mode
The HT23C256 has lower current consumption,
controlled by the chip enable input (CE/CE).
When a low/high level is applied to the CE/CE
input regardless of the output enable
(OE/OE/NC) states the chip will enter the
standby mode.
Data read mode
When both the chip enable (CE/CE/OE/OE1)
and the output enable (OE/OE/NC) are active,
the chip is in data read mode. Otherwise,
active CE/CE and inactive OE/OE/NC result
in deselect mode. The output will remain in
Hi-Z state.
Output load circuit
HT23C256
5
24th Aug ’98
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