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| 型號(hào)： | 24945 |
| 英文描述： | Implementing SDLC on the Am186CC or Am186CH Microcontroller Application Note? 76.1KB (PDF) |
| 中文描述： | 實(shí)施的SDLC的Am186CC或Am186CH微控制器應(yīng)用筆記？ 76.1KB（PDF格式） |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 76K |
| 代理商： | 24945 |
Implementing SDLC on the Am186CC or Am186CH Microcontroller
2
SDLC
SDLC is a layer 2 protocol developed by IBM. It is very
similar to HDLC with a slight difference.
Difference between HDLC and SDLC
To the HDLC controller of the Am186CC and
Am186CH microcontrollers, SDLC is almost the same
as HDLC, except for the address field. HDLC uses a
16-bit address, while SDLC uses an 8-bit address. This
is not a problem in the transmitting direction, because
the address field is filled by the programmer; the HDLC
controller just sends it out (with zero insertion). How-
ever, in the receiving direction, the HDLC controller
performs address recognition to determine whether or
not to accept the current frame, so the receiver needs
to know how many address bits there are.
In most cases, HDLC and SDLC are used in a point-to-
point link, where destination address is not needed at
all. In these cases, the address recognition function of
the HDLC controller is not used for either protocol.
Address Recognition
When one of the HDLC channels in the Am186CC or
Am186CH microcontroller is enabled for receiving, it
waits for an opening flag. When the receiver detects
the flag, it compares the frame address (the first 16
data bits following the flag) against the user-pro-
grammed addresses. Each HDLC channel has four
16-bit address match registers (the HxA0–HxA3 regis-
ters) and four corresponding 16-bit address mask reg-
isters (the HxA0MSK–HxA3MSK registers). Table 1
lists these registers for HDLC channel A. The mask
register determines which bits of the first 16 data bits in
the frame should be compared to the corresponding
address register and which bits should be ignored.
The HDLC controller compares the received address
field (16-bit) to the user-defined values (in the chan-
nel’s four address registers) and masks the result with
the address mask (in the corresponding address mask
register). If all unmasked bits of at least one address
(out of four) match, the receiver accepts the frame; oth-
erwise, it discards the frame and starts looking for the
next flag. Each HDLC channel can recognize up to four
different mask and address sets. Each set can select
either one address or multiple addresses, using either
8-bit or 16-bit addressing.
Note:
Register bits 7–0 correspond to the first byte re-
ceived, and bits 15–8 correspond to the second byte
received.
The HDLC controller can also recognize broadcast ad-
dress frames (all bits = 1), if one address match regis-
ter is written with all bits set to 1.
For 8-bit addresses of SDLC, just mask (clear) the
eight high-order bits in one of the HxA0MSK–
HxA3MSK registers.
16-Bit Address Recognition Example
To accept a frame that begins with the three bytes 7Eh
(flag), 5Bh, and ACh, using 16-bit address recognition,
one of the HxA0–HxA3 registers should contain
AC5Bh, and the corresponding HxAnMSK register
should contain FFFFh.
The configuration in Figure 2 recognizes:
I
One 16-bit address: AC5B
I
The 16-bit broadcast address: FFFF
I
A set of 16-bit addresses: xx5C (x=0–F)
I
A set of 16-bit addresses: AC60–AC6F
Figure 2.
16-Bit Address Matching Example
Table 1.
HDLC Channel A Address Registers
Offset
Mnemonic
Register Name
22h
HAA0
HDLC Channel A Address 0
24h
HAA0MSK
HDLC Channel A Address Mask 0
26h
HAA1
HDLC Channel A Address 1
28h
HAA1MSK
HDLC Channel A Address Mask 1
2Ah
HAA2
HDLC Channel A Address 2
2Ch
HAA2MSK
HDLC Channel A Address Mask 2
2Eh
HAA3
HDLC Channel A Address 3
30h
HAA3MSK
HDLC Channel A Address Mask 3
Frame with 16-bit Address
Address
5B
Flag
7E
Address
AC
Control
9C
Etc.
Match and Mask Register Contents
HxA0 AC5B
HxA0MSK FFFF
HxA1 FFFF
HxA1MSK FFFF
HxA2 AC5C
HxA2MSK 00FF
HxA3 AC6x
HxA3MSK FFF0
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