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參數(shù)資料
| 型號： | 24AA00-P |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 128 Bit I 2 C? Bus Serial EEPROM |
| 中文描述： | 128位的I 2 C？總線串行EEPROM |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 264K |
| 代理商： | 24AA00-P |
24AA00/24LC00/24C00
DS21178D-page 4
2003 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24AA00-SN | 128 Bit I 2 C? Bus Serial EEPROM |
| 24AA00-ST | 128 Bit I 2 C? Bus Serial EEPROM |
| 24AA00T-EP | 128 Bit I 2 C? Bus Serial EEPROM |
| 24AA00T-P | 128 Bit I 2 C? Bus Serial EEPROM |
| 24AA00T-SN | 128 Bit I 2 C? Bus Serial EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24AA00-SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:128 Bit I 2 C? Bus Serial EEPROM |
| 24AA00-ST | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:128 Bit I 2 C? Bus Serial EEPROM |
| 24AA00T/OT | 功能描述:電可擦除可編程只讀存儲器 16byte 128kb 1.8V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24AA00T-/OT | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K Software Addressable I2C⑩ Serial EEPROM |
| 24AA00T-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K Software Addressable I2C⑩ Serial EEPROM |
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