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參數(shù)資料
| 型號： | 24AA025TIMS |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | EEPROM |
| 英文描述： | 2K I2C Serial EEPROM |
| 中文描述： | 2K的I2C串行EEPROM |
| 文件頁數(shù)： | 9/22頁 |
| 文件大小： | 254K |
| 代理商： | 24AA025TIMS |
2004 Microchip Technology Inc.
DS21210G-page 9
24AA024/24LC024/24AA025/24LC025
8.0
READ OPERATIONS
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
1
’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24AA024/24LC024/24AA025/24LC025 contains
an address counter that maintains the address of the
last word accessed, internally incremented by one.
Therefore, if the previous read access was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with the R/W bit set to ‘
1
’, the 24AA024/
24LC024/24AA025/24LC025 issues an acknowledge
and transmits the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition
and
the
24AA024/24LC024/24AA025/
24LC025 discontinues transmission (Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AA024/24LC024/24AA025/24LC025
as part of a write operation. Once the word address is
sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
but not before the internal address pointer is set. The
master then issues the control byte again, but with the
R/W bit set to a ‘
1
’. The 24AA024/24LC024/24AA025/
24LC025 will then issue an acknowledge and transmits
the eight bit data word. The master will not acknowl-
edge the transfer but does generate a Stop condition
and the 24AA024/24LC024/24AA025/24LC025 dis-
continues transmission (Figure 8-2). After this com-
mand, the internal address counter will point to the
address location following the one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24AA024/24LC024/
24AA025/24LC025 transmits the first data byte, the
master issues an acknowledge (as opposed to a Stop
condition in a random read). This directs the 24AA024/
24LC024/24AA025/24LC025 to transmit the next
sequentially-addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24AA024/24LC024/
24AA025/24LC025 contains an internal address
pointer that is incremented by one upon completion of
each operation. This address pointer allows the entire
memory contents to be serially read during one
operation.
The
internal
automatically roll over from address 0FFh to address
000h.
address
pointer
will
FIGURE 8-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
P
S
S
T
O
P
CONTROL
BYTE
S
T
A
R
T
DATA
A
C
K
O
A
C
K
N
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