1995 Microchip Technology Inc.
DS21052E-page 5
24AA01/02
4.0
BUS CHARACTERISTICS
4.1
Slave Address
The 24AA01/02 are software-compatible with older
devices such as 24C01A, 24C02A, 24LC01, and
24LC02. A single 24AA02 can be used in place of two
24LC01's, for example, without any modifications to
software. The “chip select” portion of the control byte
becomes a don't care.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24AA01/02, followed by three don't
care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24AA01/02 (see
Figure 4-1).
The 24AA01/02 monitors the bus for its corresponding
slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 4-1:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Chip Select
R/W
Read
Write
1010
1010
XXX
XXX
1
0
START
READ/WRITE
SLAVE ADDRESS
R/W
1
0
1
0
X
X
X
A
X = don't care
5.0
WRITE OPERATION
5.1
Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24AA01/02. After
receiving another acknowledge signal from the
24AA01/02 the master device will transmit the data
word to be written into the addressed memory location.
The 24AA01/02 acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24AA01/02 will not
generate acknowledge signals (see Figure 5-1).
5.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA01/02 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to eight data bytes to the
24AA01/02 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
FIGURE 5-1:
BYTE WRITE
S
T
O
P
SDA LINE
P
DATA
S
T
A
R
T
CONTROL
BYTE
S
WORD
ADDRESS
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K