
1996 Microchip Technology Inc.
DS21053E-page 3
24AA04/08
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Standard Mode
V
CC
Fast Mode
= 4.5-5.5V
Units
Remarks
Min
—
4000
4700
—
—
4000
Max
100
—
—
1000
300
—
Min
—
600
1300
—
—
600
Max
400
—
—
300
300
—
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Fclk
Thigh
Tlow
Tr
Tf
T
HD
kHz
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
:
STA
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup time T
Output valid from clock
Bus free time
T
SU
:
STA
4700
—
600
—
ns
T
T
HD
:
:
:
DAT
0
—
—
—
0
—
—
—
900
—
ns
ns
ns
ns
ns
SU
DAT
250
4000
—
4700
100
600
—
1300
SU
T
T
STO
AA
3500
—
(Note 2)
Time the bus must be free before
a new transmission can start
(Note 1), C
B
≤
100 pF
BUF
Output fall time from V
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Endurance
IH
T
OF
—
250
20 + 0.1
C
B
—
250
ns
T
SP
—
50
50
ns
(Note 3)
T
WR
—
—
10M
1M
10
—
—
10M
1M
10
—
ms
Byte or Page mode
cycles 25
°
C, Vcc = 5.0V, Block Mode
(Note 4)
24AA04
24AA08
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
B
= total capacitance of one bus line in pF.
I
specification for standard operation.
T
SU
:
STA
T
F
T
LOW
T
HIGH
T
R
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
HD
:
STA
T
BUF
T
AA
T
AA
T
SP
T
HD
:
STA
SCL
SCL
IN
SCL
OUT
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