參數(shù)資料
型號: 24AA160-ISN
廠商: Microchip Technology Inc.
英文描述: 8K/16K 1.8V SPI Bus Serial EEPROM
中文描述: 8K/16K 1.8V的SPI總線串行EEPROM
文件頁數(shù): 4/12頁
文件大?。?/td> 92K
代理商: 24AA160-ISN
25AA080/160
DS21146D-page 4
Preliminary
1996 Microchip Technology Inc.
TABLE 1-3:
AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted.
VCC = +1.8V to 5.5V
Commercial (C):
Tamb = 0C to +70C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Symbol
Parameter
Min
Max
Units
Test Conditions
fSCK
Clock Frequency
100
250
500
100
250
500
250
500
500
30
50
50
50
100
100
150
250
475
150
250
475
50
0
3
2
1
2
2
150
250
475
200
250
500
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
μ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
(Note 1)
(Note 1)
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tCSS
CS Setup Time
tCSH
CS Hold Time
tCSD
CS Disable Time
tSU
Data Setup Time
tHD
Data Hold Time
tR
tF
tHI
CLK Rise Time
CLK Fall Time
Clock High Time
s
s
tLO
Clock Low Time
tCLD
tV
Clock Delay Time
Output Valid from
Clock Low
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
tHO
tDIS
Output Hold Time
Output Disable Time
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V
VCC=2.5V to 4.5V
VCC=1.8V to 2.5V
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
VCC=4.5V to 5.5V (Note 1)
VCC=2.5V to 4.5V (Note 1)
VCC=1.8V to 2.5V (Note 1)
(Note 2)
25
°
C, Vcc = 5.0V, Block Mode (Note 3)
tHS
HOLD Setup Time
100
100
200
100
100
200
100
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHH
HOLD Hold Time
tHZ
HOLD Low to Output High-Z
tHV
HOLD High to Output Valid
100
150
200
ns
ns
ns
tWC
Internal Write Cycle Time
Endurance
10M
5
ms
E/W
Cycles
Note 1:
This parameter is periodically sampled and not 100% tested.
twc begins on the rising edge of CS after a valid write sequence and ends when the internal self-timed write cycle is com-
plete.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our BBS or website.
2:
3:
This document was created with FrameMaker 4 0 4
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