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參數(shù)資料
| 型號(hào)： | 24AA164 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 16K 1.8V Cascadable CMOS serial EEPROMs(16K位,1.8V層疊IIC串行EEPROM) |
| 中文描述： | 16K的1.8級(jí)聯(lián)的CMOS串行EEPROM（16K的位，1.8層疊進(jìn)口證串行EEPROM的） |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 24AA164 |
1995 Microchip Technology Inc.
DS21100C-page 7
24AA164
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24AA164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24AA164 to transmit the next sequentially
addressed 8 bit word (see Figure 9-3).
To provide sequential reads the 24AA164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
8.4
Noise Protection
The 24AA164 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
9.0
PIN DESCRIPTIONS
9.1
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 10K
for 100 kHz, 1K
for 400
kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
9.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
9.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read opera-
tions are not affected.
This feature allows the user to use the 24AA164 as a
serial ROM when WP is enabled (tied to V
CC
).
9.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24AA164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24AA164s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
Note:
The level on A1 is compared to the inverse
of the slave address.
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| 24AA16ISN | 16K 1.8V I 2 C O Serial EEPROM |
| 24AA16P | 16K 1.8V I 2 C O Serial EEPROM |
| 24AA16SL | 16K 1.8V I 2 C O Serial EEPROM |
| 24AA16SN | 16K 1.8V I 2 C O Serial EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24AA164/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24AA164/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24AA164P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 1.8V Cascadable I2CTM Serial EEPROM |
| 24AA164SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 1.8V Cascadable I2CTM Serial EEPROM |
| 24AA164TP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 1.8V Cascadable I2CTM Serial EEPROM |
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