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參數(shù)資料
| 型號： | 24AA164TSN |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 16K 1.8V Cascadable I2CTM Serial EEPROM |
| 中文描述： | 16K的1.8級聯(lián)I2CTM串行EEPROM |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 124K |
| 代理商： | 24AA164TSN |
1999 Microchip Technology Inc.
DS21100F-page 3
24AA164
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
T
F
Parameter
Symbol
STANDARD
MODE
V
CC
FAST MODE
= 4.5-5.5V
Units
Remarks
Min
—
4000
4700
—
—
4000
Max
100
—
—
1000
300
—
Min
—
600
1300
—
—
600
Max
400
—
—
300
300
—
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold
time
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from clock
Bus free time
F
T
T
CLK
kHz
ns
ns
ns
ns
ns
HIGH
LOW
T
R
T
F
:
STA
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
T
HD
T
SU
:
STA
4700
—
600
—
ns
T
T
T
HD
:
:
:
DAT
0
—
—
—
0
—
—
—
ns
ns
ns
SU
DAT
250
4000
100
600
SU
STO
T
T
AA
—
3500
—
—
900
—
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
BUF
4700
1300
Output fall time from V
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Endurance
IH
T
OF
—
250
20 + 0.1
C
B
—
250
ns
100 pF
T
SP
—
50
50
ns
(Note 3)
T
WR
—
—
1M
10
—
—
1M
10
—
ms
Byte or Page mode
25°C, Vcc = 5.0V, Block
Mode ((Note 4)
cycles
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
=specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
B
= total capacitance of one bus line in pF.
I
specification for standard operation.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
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