1995 Microchip Technology Inc.
DS21102C-page 7
24AA174
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24AA174 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24AA174 to transmit the next sequentially
addressed 8 bit word (see Figure 9-3).
To provide sequential reads the 24AA174 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
8.4
Noise Protection
The 24AA174 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
9.0
PIN DESCRIPTIONS
9.1
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 10K
for 100 kHz, 1K
for 400
kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
9.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
9.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read opera-
tions are not affected.
This feature allows the user to use the 24AA174 as a
serial ROM when WP is enabled (tied to V
CC
).
9.4
A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24AA174 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24AA174s may be connected to the same
bus. These pins must be connected to either V
SS
or
V
CC
.
9.5
Security Access Control
The security row is enabled by sending the control
sequence with the I
2
C slave address of 0110. Bit 0 of
the control byte must be set to a 1 for a READ OPER-
ATION or a 0 for the OTP WRITE OPERATION. The
SECURITY ACCESS DATA is always read starting at
byte 0 for N bytes up to and including byte 15. (See
Figure 8-1).
9.6
Security Access Write
The S.A.W. data is written to the device using a normal
page write following the proper control access
sequence. Upon receiving the final stop bit, the internal
write sequence will commence. At the completion of
the internal write sequence a fuse will be set disabling
the write function for the 16 byte security page.
9.7
Security Access Read
The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a 1. The secu-
rity page read starts at data byte 0.
Note:
The level on A1 is compared to the inverse
of the slave address.