參數(shù)資料
型號: 24AA515
廠商: Microchip Technology Inc.
英文描述: 512K I2C CMOS Serial EEPROM
中文描述: 為512k的I2C的CMOS串行EEPROM
文件頁數(shù): 3/22頁
文件大?。?/td> 285K
代理商: 24AA515
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 3
24AA515/24LC515/24FC515
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
V
CC
= +1.8V to 5.5V
T
A
= -40°C to +85°C
Param.
No.
Sym
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
100
400
1000
1000
300
300
300
100
3500
900
400
250
250
kHz
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
All except, 24FC515
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
(Note 2)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
All except, 24FC515
(Note 1)
24FC515
(Note 1)
2
T
HIGH
Clock high time
4000
600
500
4700
1300
500
4000
600
250
4700
600
250
0
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
4700
1300
500
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note 1)
ns
5
T
F
SDA and SCL fall time
(Note 1)
Start condition hold time
ns
6
T
HD
:
STA
ns
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
(Note 2)
ns
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
C
B
100 pF
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance Model which can be obtained from Microchip’s web site @www.microchip.com.
ns
15
T
OF
10 + 0.1C
B
ns
16
T
SP
50
ns
All except, 24FC515
(Notes 1 and 3)
17
18
T
WC
1 M
5
ms
cycles
25°C, V
CC
= 5.0V, Block mode
(Note 4)
Note 1:
2:
3:
4:
相關PDF資料
PDF描述
24LC515 512K I2C CMOS Serial EEPROM
24FC65-IP 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC65-ISM 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC65-P 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC65-SM 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM
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