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參數(shù)資料
| 型號： | 24C00T-IP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 128 Bit I 2 C? Bus Serial EEPROM |
| 中文描述： | 128位的I 2 C？總線串行EEPROM |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 264K |
| 代理商： | 24C00T-IP |
2003 Microchip Technology Inc.
DS21178D-page 7
24AA00/24LC00/24C00
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W =
0
). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
FIGURE 7-2:
BYTE WRITE
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W =
0
Did Device
Acknowledge
(ACK = 0)
Next
Operation
NO
YES
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
1
0
X
1
0
X
X
X
X = Don’t Care Bit
X
X
X
0
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