參數(shù)資料
型號: 24C01B
廠商: Microchip Technology Inc.
英文描述: 1K 5.0V IIC serial EEPROMs(1K位,5.0V,IIC串行EEPROM)
中文描述: 一千5.0V進口證(每1000位和5.0V串行EEPROM,串行EEPROM的國際進口許可證)
文件頁數(shù): 6/12頁
文件大?。?/td> 162K
代理商: 24C01B
24C01B/02B
DS21233A-page 6
Preliminary
1997 Microchip Technology Inc.
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
FIGURE 5-1:
ACKNOWLEDGE POLLING
FLOW
6.0
WRITE PROTECTION
The 24C01B/02B can be used as a serial ROM when
the WP pin is connected to V
CC
. Programming will be
inhibited and the entire memory will be write-protected.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
7.1
Current Address Read
The 24C01B/02B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24C01B/
02B issues an acknowledge and transmits the eight bit
data word. The master will not acknowledge the trans-
fer but does generate a stop condition and the 24C01B/
02B discontinues transmission (Figure 7-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01B/02B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C01B/02B will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C01B/02B
discontinues transmission (Figure 7-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C01B/02B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24C01B/02B to transmit the next sequen-
tially addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24C01B/02B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24C01B/02B employs a V
CC
threshold detector cir-
cuit which disables the internal erase/write logic if the
V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)
Next
Operation
NO
YES
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