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參數(shù)資料
| 型號： | 24C02A-ISL |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 中文描述： | 1K/2K/4K 5.0VI 2二氧化碳串行EEPROM |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 77K |
| 代理商： | 24C02A-ISL |
24C01A/02A/04A
DS11183D-page 8
1996 Microchip Technology Inc.
FIGURE 9-3:
SEQUENTIAL READ
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA n
DATA n + 1
DATA n + 2
DATA n + X
A
C
K
A
C
K
A
C
K
10.0
PIN DESCRIPTION
10.1
A0, A1, A2 Chip Address Inputs
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true. For 24C04 A0 is no
function.
Up to eight 24C01A/02A's or up to four 24C04A's can
be connected to the bus.
These inputs must be connected to either V
SS
or V
CC
.
10.2
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10K
).
For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
10.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
10.4
WP Write Protection
This pin must be connected to either V
CC
or V
SS
for
24C02A or 24C04A. It has no effect on 24C01A.
If tied to V
CC
, PROGRAM operations onto the upper
memory block will not be executed. Read operations
are possible.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory).
This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.
Note 1:
A “page” is defined as the maximum num-
ber of bytes that can be programmed in a
single write cycle. The 24C04A page is 8
bytes long; the 24C01A/02A page is 2
bytes long.
Note 2:
A “block” is defined as a continuous area
of memory with distinct boundaries. The
address pointer can not cross the bound-
ary from one block to another. It will how-
ever, wrap around from the end of a block
to the first location in the same block. The
24C04A has two blocks, 256 bytes each.
The 24C01A and 24C02A each have only
one block.
相關(guān)PDF資料 |
PDF描述 |
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| 24C02A-ISM | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-ISN | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-P | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-SL | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-SM | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24C02A-ISM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-ISN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-SL | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C02A-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
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