24C01B/02B
1997 Microchip Technology Inc.
Preliminary
DS21233A-page 3
FIGURE 1-2:
BUS TIMING DATA
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across the
specified operating ranges unless
otherwise noted
Vcc = 4.5V to 5.5V
Automotive (E):
Tamb = -40C to +125C,
Parameter
Symbol
Min.
Max.
Units
Remarks
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
T
T
CLK
—
100
—
—
1000
300
—
kHz
ns
ns
ns
ns
ns
HIGH
4000
4700
—
—
4000
LOW
T
R
T
F
:
STA
(Note 1)
(Note 1)
After this period the first clock pulse is
generated
Only relevant for repeated
START condition
(Note 2)
T
HD
START condition setup time
T
SU
:
STA
4700
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
HD
:
:
:
DAT
0
—
—
—
ns
ns
ns
ns
ns
SU
DAT
250
4000
—
4700
SU
T
T
STO
AA
3500
—
(Note 2)
Time the bus must be free before a new
transmission can start
(Note 1), CB
≤
100 pF
BUF
Output fall time from V
minimum to V
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
IH
IL
maximum
T
OF
—
250
ns
T
SP
—
50
ns
(Note 3)
T
WR
—
—
1M
10
—
ms
Byte or Page mode
25
°
C, Vcc = 5.0V, Block Mode (Note 4)
cycles
SCL
SDA
IN
SDA
OUT
T
HD
:
STA
T
SU
:
STA
T
F
T
HIGH
T
R
T
SU
:
STO
T
SU
:
DAT
T
HD
:
DAT
T
BUF
T
AA
T
HD
:
STA
T
AA
T
SP
T
LOW