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參數(shù)資料
| 型號(hào)： | 24C04AP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | IC |
| 中文描述： | 集成電路 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | 24C04AP |
1998 Microchip Technology Inc.
DS11183E-page 7
24C04A
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 7-1 for ow diagram.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
8.0
WRITE PROTECTION
Programming of the upper half of the memory will not
take place if the WP pin is connected to VCC (+5.0V).
The device will accept slave and word addresses but if
the memory accessed is write protected by the WP pin,
the 24C04A will not generate an acknowledge after the
rst byte of data has been received, and thus the pro-
gram cycle will not be started when the STOP condition
is asserted.
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