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參數(shù)資料
| 型號： | 24C128 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 128K IIC CMOS serial EEPROM(4.5~5.5V,128K位,IIC CMOS 串行EEPROM) |
| 中文描述： | 128K的國際進口證的CMOS串行EEPROM（4.5?5.5V的，128K的位，進口證的CMOS串行EEPROM的） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 227K |
| 代理商： | 24C128 |
24xx128
DS21191A-page 6
Preliminary
1997 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the
24xx128 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24xx128 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A13…A0 are used, the upper two address bits are
don’t care bits. The upper address bits are transferred
first, followed by the less significant bits.
Following the start condition, the 24xx128 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24xx128 will select a read or
write operation.
FIGURE 5-1:
CONTROL BYTE FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 1 Mbit by add-
ing up to eight 24xx128's on the same bus. In this case,
software can use A0 of the control byte as address bit
A14; A1, as address bit A15; and A2, as address bit
A16. It is not possible to sequentially read across
device boundaries.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A2
A1
A0
S
ACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1
0
1
0
A
2
A
1
A
0R/W
X
X
A
11
A
10
A
9
A
7
A
0
A
8
A
12
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
CONTROL
CODE
CHIP
SELECT
BITS
X = Don’t Care Bit
A
13
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