參數(shù)資料
型號: 24FC32-P
廠商: Microchip Technology Inc.
英文描述: 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
中文描述: 32K的5.0V 1兆赫的I 2 C串行EEPROM智能
文件頁數(shù): 8/12頁
文件大?。?/td> 99K
代理商: 24FC32-P
24FC32
DS21126B-page 3-8
1996 Microchip Technology Inc.
6.3
Contiguous Addressing Across
Multiple Devices
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24FC32's on the same bus. In
this case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14.
6.4
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24FC32 transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24FC32 to transmit the
next sequentially addressed 8 bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will
generate a stop condition.
To provide sequential reads the 24FC32 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The address pointer, however,
will not roll over from address 07FF to address 0000. It
will roll from 07FF to unused memory space.
6.5
Noise Protection
The SCL and SDA inputs incorporate Schmitt triggers
which suppress noise spikes to ensure proper device
operation even on a noisy bus.
FIGURE 6-2:
RANDOM READ
FIGURE 6-3:
SEQUENTIAL READ
BUS
MASTER
SDA LINE
BUS
CONTROL
BYTE
WORD
ADDRESS (1)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
ACTIVITY:
ACTIVITY:
A
C
K
N
O
DATA n
0 0 0 0
WORD
ADDRESS (0)
S
T
A
R
T
CONTROL
BYTE
A
C
K
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA n
DATA n + 1
DATA n + 2
DATA n + X
A
C
K
A
C
K
A
C
K
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