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參數(shù)資料
| 型號： | 24FC65-IP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 中文描述： | 64K的5.0V 1兆赫的I 2 C串行EEPROM智能 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 140K |
| 代理商： | 24FC65-IP |
24FC65
DS21125B-page 8
1996 Microchip Technology Inc.
byte would be 10XX0011. After the third byte is sent to
the device, it will acknowledge and a STOP bit is then
sent by the master to complete the command.
During a normal write sequence, if an attempt is made
to write to a protected address, no data will be written
and the device will not report an error or abort the
command. If a write command is attempted across a
secure boundary, unprotected addresses will be written
and protected addresses will not.
5.8
Security Configuration Read
The status of the secure portion of memory can be read
by using the same technique as programming this
option except the READ bit (bit 6) of the configuration
byte is set to a one. After the configuration byte is sent,
the device will acknowledge and then send two bytes of
data to the master just as in a normal read sequence.
The master must acknowledge the first byte and not
acknowledge the second, and then send a stop bit to
end the sequence. The upper four bits of both of these
bytes will always be read as '1's. The lower four bits of
the first byte contains the starting secure block. The
lower four bits of the second byte contains the number
of secure blocks. The default starting secure block is
fifteen and the default number of secure blocks is zero
(Figure 8-1).
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the STOP for a write command has
been issued from the master, the device initiates the
internally timed write cycle. ACK polling can be initiated
immediately. This involves the master sending a START
followed by the control byte for a write command (R/W
= 0). If the device is still busy with the write cycle, then
no ACK will be returned. If the cycle is complete, then
the device will return the ACK and the master can then
proceed with the next read or write command. See
Figure 6-1 for flow diagram.
FIGURE 6-1:
ACKNOWLEDGE POLLING
FLOW
Did Device
Acknowledge
(ACK = 0)
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24FC65-ISM | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-P | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-SM | 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65 | 64K 5.0V 1MHz CMOS Smart Serial EEPROMs(4.5~5.5V,64K位,10M次擦寫周期,IIC智能串行EEPROM) |
| 24HCA | surface mount silicon Zener diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24FC65-ISM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC65T-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
| 24FC65T-/SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:64K 5.0V 1 MHz I2C⑩ Smart Serial⑩ EEPROM |
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