參數(shù)資料
    型號(hào): 24FC65-P
    廠商: Microchip Technology Inc.
    英文描述: 64K 5.0V 1 MHz I 2 C Smart Serial EEPROM
    中文描述: 64K的5.0V 1兆赫的I 2 C串行EEPROM智能
    文件頁(yè)數(shù): 4/16頁(yè)
    文件大?。?/td> 140K
    代理商: 24FC65-P
    24FC65
    DS21125B-page 4
    1996 Microchip Technology Inc.
    2.0
    FUNCTIONAL DESCRIPTION
    The 24FC65 supports a bidirectional two-wire bus and
    data transmission protocol. A device that sends data
    onto the bus is defined as transmitter, and a device
    receiving data as receiver. The bus must be controlled
    by a master device which generates the serial clock
    (SCL), controls the bus access, and generates the
    START and STOPs, while the 24FC65 works as slave.
    Both master and slave can operate as transmitter or
    receiver but the master device determines which mode
    is activated.
    3.0
    BUS CHARACTERISTICS
    The following
    Data transfer may be initiated only when the bus is
    not busy.
    During data transfer, the data line must remain
    stable whenever the clock line is HIGH. Changes
    in the data line while the clock line is HIGH will be
    interpreted as a START or STOP.
    Accordingly, the following bus conditions have been
    defined (Figure 3-1).
    bus protocol
    has been defined:
    3.1
    Bus not Busy (A)
    Both data and clock lines remain HIGH.
    3.2
    Start Data Transfer (B)
    A HIGH to LOW transition of the SDA line while the
    clock (SCL) is HIGH determines a START. All
    commands must be preceded by a START.
    3.3
    Stop Data Transfer (C)
    A LOW to HIGH transition of the SDA line while the
    clock (SCL) is HIGH determines a STOP. All operations
    must be ended with a STOP.
    3.4
    Data Valid (D)
    The state of the data line represents valid data when,
    after a START, the data line is stable for the duration of
    the HIGH period of the clock signal.
    The data on the line must be changed during the LOW
    period of the clock signal. There is one clock pulse per
    bit of data.
    Each data transfer is initiated with a START and
    terminated with a STOP. The number of the data bytes
    transferred between the START and STOPs is
    determined by the master device.
    3.5
    Acknowledge
    Each receiving device, when addressed, is obliged to
    generate an acknowledge after the reception of each
    byte. The master device must generate an extra clock
    pulse which is associated with this acknowledge bit.
    A device that acknowledges must pull down the SDA
    line during the acknowledge clock pulse in such a way
    that the SDA line is stable LOW during the HIGH period
    of the acknowledge related clock pulse. Of course,
    setup and hold times must be taken into account.
    During reads, a master must signal an end of data to
    the slave by NOT generating an acknowledge bit on the
    last byte that has been clocked out of the slave. In this
    case, the slave (24FC65) must leave the data line
    HIGH to enable the master to generate the STOP.
    Note:
    The 24FC65 does not generate any
    acknowledge bits if an internal program-
    ming cycle is in progress.
    FIGURE 3-1:
    DATA TRANSFER SEQUENCE ON THE SERIAL BUS
    SCL
    SDA
    (A)
    (B)
    START
    Condition
    (C)
    (A)
    (D)
    (D)
    Address
    or
    Acknowledge
    Valid
    Data Allowed
    to Change
    STOP
    Condition
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