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| 型號(hào)： | 24LC00-EP |
| 廠(chǎng)商： | Microchip Technology Inc. |
| 英文描述： | 128 Bit I 2 C? Bus Serial EEPROM |
| 中文描述： | 128位的I 2 C？總線(xiàn)串行EEPROM |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 264K |
| 代理商： | 24LC00-EP |
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2003 Microchip Technology Inc.
DS21178D-page 3
24AA00/24LC00/24C00
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Commercial (C):
Industrial (I):
Automotive (E):
T
A
= 0°C to +70°C,
T
A
= -40°C to +85°C,
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
V
CC
= 1.8V to 5.5V
V
CC
= 1.8V to 5.5V
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
—
—
—
100
100
400
—
—
—
—
—
—
1000
1000
300
300
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
3500
900
—
—
—
250
kHz
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
(Note 1)
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
(Note 2)
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
4.5V
≤
Vcc
≤
5.5V (E Temp range)
1.8V
≤
Vcc
≤
4.5V
4.5V
≤
Vcc
≤
5.5V
(Note 1)
, CB
≤
100 pF
Clock high time
T
HIGH
4000
4000
600
4700
4700
1300
—
—
—
—
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
—
—
—
4700
4700
1300
20+0.1
CB
—
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
(Note 1)
T
R
ns
SDA and SCL fall time
Start condition hold time
T
F
T
HD
:
STA
ns
ns
Start condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
Stop condition setup time
T
SU
:
STO
ns
Output valid from clock
(Note 2)
T
AA
ns
Bus free time: Time the bus must
be free before a new transmis-
sion can start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on www.microchip.com.
T
BUF
ns
T
OF
ns
T
SP
50
ns
(Notes 1, 3)
T
WC
—
1M
4
—
ms
cycles
(Note 4)
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