參數(shù)資料
型號: 24LC014T-I/MSG
元件分類: PROM
英文描述: 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: LEAD FREE, PLASTIC, MO-187, MSOP-8
文件頁數(shù): 7/9頁
文件大?。?/td> 876K
代理商: 24LC014T-I/MSG
2005 Microchip Technology Inc.
DS21930A-page 7
24AAXX/24LCXX/24FCXX
TABLE 2-3:
AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02C
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Commercial (C):
T
A =
0°C to +70°C,
V
CC = 1.8V to 5.5V
Industrial (I):
T
A = -40°C to +85°C,
V
CC = 1.8V to 5.5V
Automotive (E):
T
A = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
100
400
kHz
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Clock high time
T
HIGH
4000
600
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Clock low time
T
LOW
4700
1300
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
SDA and SCL rise time
T
R
1000
300
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
SDA and SCL fall time
T
F
—300
ns
Start condition hold time
T
HD:STA
4000
600
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Start condition setup time
T
SU:STA
4700
600
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Data input hold time
T
HD:DAT
0—
ns
Data input setup time
T
SU:DAT
250
100
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Stop condition setup time
T
SU:STO
4000
600
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Output valid from clock
T
AA
3500
900
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
T
BUF
4700
1300
ns
4.5V
≤ Vcc ≤ 5.5V (E Temp range)
1.8V
≤ Vcc ≤ 4.5V
4.5V
≤ Vcc ≤ 5.5V
Output fall time from V
IH
minimum to V
IL maximum
T
OF
20+0.1
CB
250
ns
(Note 1), CB
≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—50
ns
Write cycle time
T
WC
—4
1.5
ms
24XX00
24C01C, 24C02C
Endurance
1,000,000
cycles
Note 1:
Not 100% tested. C
B = total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained at www.microchip.com.
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