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參數(shù)資料
| 型號： | 24LC01B |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K 2.5V CMOS serial EEPROM(1K位、8字節(jié)頁面緩沖器、有硬件寫保護(hù)、10M次擦寫周期、2.5-5.5V工作電壓、CMOS IIC串行EEPROM) |
| 中文描述： | 一千為2.5V的CMOS串行EEPROM（每1000位，8字節(jié)頁面緩沖器，有硬件寫保護(hù)，1000萬次擦寫周期,2.5 - 5 .5 V工作電壓，國際進(jìn)口證的CMOS串行EEPROM的） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 111K |
| 代理商： | 24LC01B |
1995 Microchip Technology Inc.
DS20071G-page 5
24LC01B/02B
4.0
BUS CHARACTERISTICS
4.1
Slave Address
The 24LC01B/02B are software-compatible with older
devices such as 24C01A, 24C02A, 24LC01, and
24LC02. A single 24LC02B can be used in place of two
24LC01's, for example, without any modifications to
software. The “chip select” portion of the control byte
becomes a don't care.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24LC01B/02B, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC01B/02B (see
Figure 4-1).
The 24LC01B/02B monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 4-1:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Chip
Select
R/W
Read
Write
1010
1010
XXX
XXX
1
0
START
READ/WRITE
SLAVE ADDRESS
R/W
1
0
1
0
X
X
X
A
X = don't care
5.0
WRITE OPERATION
5.1
Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC01B/02B. After
receiving another acknowledge signal from the
24LC01B/02B the master device will transmit the data
word to be written into the addressed memory location.
The 24LC01B/02B acknowledges again and the mas-
ter generates a stop condition. This initiates the inter-
nal write cycle, and during this time the 24LC01B/02B
will not generate acknowledge signals (see Figure 5-
1).
5.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LC01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
FIGURE 5-1:
BYTE WRITE
S
T
O
P
SDA LINE
P
DATA
S
T
A
R
T
CONTROL
BYTE
S
WORD
ADDRESS
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
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相關(guān)代理商/技術(shù)參數(shù) |
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| 24LC01B/MS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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| 24LC01B-/OT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24LC01B/P | 功能描述:電可擦除可編程只讀存儲器 128x8 - 1.8V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC01B-/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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