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參數(shù)資料
| 型號： | 24LC174 |
| 英文描述： | Serial EEPROM |
| 中文描述： | 串行EEPROM |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 163K |
| 代理商： | 24LC174 |
24LC174
DS21101G-page 8
1999 Microchip Technology Inc.
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10K
for 100 kHz, 2 K for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low.
Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read opera-
tions are not affected.
This feature allows the user to use the 24LC174 as a
serial ROM when WP is enabled (tied to Vcc).
8.4
A0, A1, A2
These pins are used to congure the proper chip
address in multiple-chip applications (more than one
24LC174 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24LC174s may be connected to the same
bus. These pins must be connected to either VSS or
VCC.
Note:
The level on A1 is compared to the inverse
of the slave address.
8.5
Security Access Control
The security row is enabled by sending the control
sequence with the I2C slave address of 0110. Bit 0 of
the control byte must be set to a one for a READ
OPERATION or a zero for the OTP WRITE OPERA-
TION. The SECURITY ACCESS DATA is always read
starting at byte 0 for N bytes up to and including byte
15. (See Figure 8-3).
8.6
Security Access Write
The S.A.W. data is written to the device using a normal
page write following the proper control access
sequence. Upon receiving the nal stop bit, the internal
write sequence will commence. At the completion of
the internal write sequence a fuse will be set disabling
the write function for the 16 byte security page.
8.7
Security Access Read
The security access read is accomplished by executing
the normal read sequences, following the security
access control sequence with bit 0 set to a one. The
security page read starts at data byte 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC174/P | 制造商:Microchip Technology Inc 功能描述:2K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 24LC174-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 2.5V Cascadable I2C⑩ Serial EEPROM with OTP Security Page |
| 24LC174/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24LC174-/SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 2.5V Cascadable I2C⑩ Serial EEPROM with OTP Security Page |
| 24LC174I/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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