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參數(shù)資料
| 型號： | 24LC32AISM |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 186K |
| 代理商： | 24LC32AISM |
1999 Microchip Technology Inc.
DS21144D-page 9
24LC32A
7.0
PIN DESCRIPTIONS
7.1
A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24LC32A for multi-
ple device operation and conform to the 2-wire bus
standard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
7.2
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10K
for 100 kHz, 2 K for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
7.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
7.4
WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-FFF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
8.0
NOISE PROTECTION
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.
9.0
POWER MANAGEMENT
This design incorporates a power standby mode when
the device is not in use and automatically powers off
after the normal termination of any operation when a
stop bit is received and all internal functions are com-
plete. This includes any error conditions, i.e., not
receiving an acknowledge or stop condition per the 2-
wire bus specification. The device also incorporates
VDD monitor circuitry to prevent inadvertent writes
(data corruption) during low-voltage conditions. The
VDD monitor circuitry is powered off when the device is
in standby mode in order to further reduce power con-
sumption.
This Material Copyrighted by Its Respective Manufacturer
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| 24LC32AT/SN | 功能描述:電可擦除可編程只讀存儲器 4kx8 - 5V - 2.5V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC32AT-E/MC | 功能描述:電可擦除可編程只讀存儲器 32K 4KX8 2.5V SER EE EXT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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| 24LC32AT-E/MS | 功能描述:電可擦除可編程只讀存儲器 4kx8 - 5V - 2.5V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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