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參數(shù)資料
| 型號： | 24LC32AXT |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 32KIC Serial EEPROM |
| 中文描述： | 32KIC串行EEPROM |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 474K |
| 代理商： | 24LC32AXT |
24LC32A MODULE
1997 Microchip Technology Inc.
DS21225A-page 5
4.0
BUS CHARACTERISTICS
The following bus protocol has been dened:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
dened (See Figure 4-1).
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse.
Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24LC32A) will leave the data line HIGH
to enable the master to generate the STOP condition.
(See Figure 4-2)
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24LC32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
SCL
SDA
START
CONDITION
DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
(A)
(B)
(D)
(C)
(A)
SCL
9
8
7
6
5
4
3
2
1
2
3
Transmitter must release the SDA line at this point allowing the Receiver
to pull the SDA line low to acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC32AXT/ST | 功能描述:電可擦除可編程只讀存儲器 4kx8 - 5/2.5V RotPin RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC32AXT-E/ST | 功能描述:電可擦除可編程只讀存儲器 4kx8 - 5/2.5V RotPin RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC32AXT-I/ST | 功能描述:電可擦除可編程只讀存儲器 4kx8 - 5/2.5V RotPin RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC32TI/SM | 制造商:Panasonic Industrial Company 功能描述:IC |
| 24LC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
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