參數(shù)資料
型號: 24LC512-EMS
廠商: Microchip Technology Inc.
英文描述: I2C⑩ Serial EEPROM Family Data Sheet
中文描述: ⑩的I2C串行EEPROM系列數(shù)據(jù)手冊
文件頁數(shù): 7/42頁
文件大?。?/td> 540K
代理商: 24LC512-EMS
2007 Microchip Technology Inc.
DS21930B-page 7
24AAXX/24LCXX/24FCXX
TABLE 2-3:
AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02C
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Industrial (I):
Automotive (E):
T
A
= -40°C to +85°C,
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
V
CC
= 1.7V to 5.5V
Parameter
Symbol
Min.
Max.
Units
Conditions
Clock frequency
F
CLK
100
100
400
1000
1000
300
300
3500
3500
900
250
kHz
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
(Note 1)
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
(Note 2)
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
(Note 1)
, CB
100 pF
Clock high time
T
HIGH
4000
4000
600
4700
4700
1300
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
4700
4700
1300
20+0.1
CB
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
(Note 1)
T
R
ns
SDA and SCL fall time
Start condition hold time
T
F
T
HD
:
STA
ns
ns
Start condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
Stop condition setup time
T
SU
:
STO
ns
Output valid from clock
(Note 2)
T
AA
ns
Bus free time: Time the bus must
be free before a new transmis-
sion can start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
T
BUF
ns
T
OF
ns
T
SP
50
ns
(Note 1)
T
WC
4
1.5
ms
24XX00
24C01C, 24C02C
(Note 3)
Endurance
Note 1:
1,000,000
cycles
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained at www.microchip.com.
2:
3:
相關(guān)PDF資料
PDF描述
24LC512-EOT I2C⑩ Serial EEPROM Family Data Sheet
24LC512-EP I2C⑩ Serial EEPROM Family Data Sheet
24AA128 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
24AA128EP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
24AA128ESM The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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