參數(shù)資料
型號(hào): 24LC512
廠商: Microchip Technology Inc.
英文描述: 512K I2C CMOS Serial EEPROM
中文描述: 為512k的I2C的CMOS串行EEPROM
文件頁(yè)數(shù): 3/26頁(yè)
文件大?。?/td> 420K
代理商: 24LC512
2004 Microchip Technology Inc.
DS21754E-page 3
24AA512/24LC512/24FC512
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
Automotive (E):
V
CC
= +1.8V to 5.5V
V
CC
= +2.5V to 5.5V
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Param.
No.
1
Sym
Characteristic
Min
Max
Units
Conditions
F
CLK
Clock frequency
100
400
1000
1000
300
300
300
100
kHz
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
< 2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
All except, 24FC512
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
(Note 2)
2
T
HIGH
Clock high time
4000
600
500
4700
1300
500
4000
600
250
4700
600
250
0
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note 1)
ns
5
T
F
SDA and SCL fall time
(Note 1)
ns
6
T
HD
:
STA
Start condition hold time
ns
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
ns
T
SU
:
DAT
Data input setup time
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
4700
1300
500
ns
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC512
All except, 24FC512
(Notes 1 and 3)
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
(Note 2)
3500
900
400
50
ns
14
T
BUF
Bus free time: Time the bus must
be free before a new transmis-
sion can start
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
ns
16
T
SP
ns
17
18
Note
T
WC
5
ms
Endurance
1,000,000
cycles
25°C
(Note 4)
1:
2:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained from Microchip’s web site: www.microchip.com.
3:
4:
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