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| 型號： | 24LCS21TISN |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 159K |
| 代理商： | 24LCS21TISN |
24LCS21
DS21127D-page 6
1999 Microchip Technology Inc.
3.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a rst in
rst out fashion.
3.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
Once switched into bi-directional Mode,
the 24LCS21 will remain in that mode until
power goes away. Removing power is the
only way to reset the 24LCS21 into the
Transmit-only mode.
Note:
The 24LCS21 does not generate any
acknowledge
bits
if
an
internal
programming cycle is in progress.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
TSU:STA
THD:STA
VHYS
TSU:STO
START
STOP
SCL
SDA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TBUF
TAA
TR
This Material Copyrighted by Its Respective Manufacturer
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LCS22A-I/P | 功能描述:電可擦除可編程只讀存儲器 VESA E-EDID RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS22A-I/PG | 功能描述:電可擦除可編程只讀存儲器 VESA E-EDID Lead Free Package RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS22A-I/SN | 功能描述:電可擦除可編程只讀存儲器 VESA E-EDID RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS22A-I/SNG | 功能描述:電可擦除可編程只讀存儲器 VESA E-EDID Lead Free Package RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS22AT-I/SN | 功能描述:電可擦除可編程只讀存儲器 VESA E-EDID RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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