24LCS41A
DS21175A-page 6
Preliminary
1996 Microchip Technology Inc.
FIGURE 2-5:
DISPLAY OPERATION PER DDC
STANDARD PROPOSED BY VESA
Communication
is idle
Is Vsync
present
No
Send EDID continuously
using Vsync as clock
tHigh to low
SCL
Yes
No
Yes
Stop sending EDID.
Switch to DDC2 mode.
Display has
optional
transit
Setor start timer
Change on
SCL, SDA or
VCLK lines
No
Yes
High - low
transiti
Reset Vsync counter = 0
No
Yes
Valid
received
DDC2 address
No
No
VCLK
cycle
Yes
Increment VCLK counter
(if appropriate)
Yes
Switch back to DDC1
mode.
DDC2 communication
idle. Display waiting for
address byte.
DDC2B
received
Yes
Receive DDC2B
command
Respond to DDC2B
command
Is display
Access.bus
TM
capable
Yes
Valiaddress
No
Yes
See Access.bus
specification to determine
correct procedure.
Yes
No
Yes
No
No
No
Display Power-on
or
DDC Circuit Powered
from +5 volts
Reset counter or timer
Counter=128 or
timer expired
High to low
transition on
SCL
No
Yes
Note 1:
The base flowchart is copyright
1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2:
The dash box and text “The 24LCS41A and ... inside dash box.” are added by Microchip Technology, Inc.
3:
Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS41A.
The 24LCS41A was designed to comply to the
portion of flowchart inside dash box.