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參數(shù)資料
| 型號： | 24WC02 |
| 英文描述： | 1K/2K/4K/8K/16K-Bit Serial E2PROM |
| 中文描述： | 1K/2K/4K/8K/16K-Bit串行E2PROM |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 45K |
| 代理商： | 24WC02 |
CAT24WC01/02/04/08/16
8
Doc. No. 25051-00 3/98 S-1
clock out data. After the CAT24WC01/02/04/08/16 re-
ceives its slave address information (with the R/
W
bit set
to one), it issues an acknowledge, then transmits the 8-
bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC01/02/04/08/16 acknowledge
the word address, the Master device resends the START
condition and the slave address, this time with the R/
W
bit set to one. The CAT24WC01/02/04/08/16 then re-
sponds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an ac-
knowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
operations. After the 24WC01/02/04/08/16 sends initial
8-bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC01/02/04/08/16 will continue to
output an 8-bit byte for each acknowledge sent by the
Master. The operation is terminated when the Master
fails to respond with an acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT24WC01/02/
04/08/16 is outputted sequentially with data from ad-
dress N followed by data from address N+1. The READ
operation address counter increments all of the
CAT24WC01/02/04/08/16 address bits so that the en-
tire memory array can be read during one operation. If
more than the E (where E = 127 for 24WC01, 255 for
24WC02, 511 for 24WC04, 1023 for 24WC08, and 2047
for 24WC16) bytes are read out, the counter will “wrap
around” and continue to clock out data bytes.
5020 FHD F10
Figure 8. Immediate Address Read Timing
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
8
9
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24WC16 | 1K/2K/4K/8K/16K-Bit Serial E2PROM |
| 24WC128 | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| 24WC32 | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| 250-8501-010 | Low-Power, SPST, Fast, CMOS Analog Switch |
| 2500-10J | Molded Unshielded RF Coils |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24WC128 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:128K-Bit I2C Serial CMOS E2PROM |
| 24WC16 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K/8K/16K-Bit Serial E2PROM |
| 24WC256KI | 制造商:CSI 功能描述: |
| 24WC32 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:32K/64K-Bit I2C Serial CMOS E2PROM |
| 24WC32P | 制造商:CATALYST 功能描述: |
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