參數(shù)資料
型號(hào): 25AA010A
廠商: Microchip Technology Inc.
英文描述: 1K SPI Bus Serial EEPROM
中文描述: 每1000 SPI總線串行EEPROM
文件頁(yè)數(shù): 10/28頁(yè)
文件大?。?/td> 362K
代理商: 25AA010A
25AA010A/25LC010A
DS21832C-page 10
Preliminary
2006 Microchip Technology Inc.
2.5
Read Status Register Instruction
(
RDSR
)
The Read Status Register instruction (
RDSR
) provides
access to the STATUS register. See Figure 2-6 for the
RDSR
timing sequence. The STATUS register may be
read at any time, even during a write cycle. The STA-
TUS register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
The
Write-In-Process (WIP)
bit indicates whether the
25XX010A is busy with a write operation. When set to
a ‘
1
’, a write is in progress, when set to a ‘
0
’, no write
is in progress. This bit is read-only.
The
Write Enable Latch (WEL)
bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
1
’, the latch allows writes to the array, when set to a
0
’, the latch prohibits writes to the array. The state of
this bit can always be updated via the
WREN
or
WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The
Block Protection (BP0 and BP1)
bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the
WRSR
instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (
RDSR
)
7
X
6
X
5
X
4
X
3
2
1
R
0
R
W/R
BP1
W/R
BP0
WEL
WIP
W/R = writable/readable. R = read-only.
SO
SI
CS
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
7
6
5
4
2
1
0
instruction
data from STATUS register
high-impedance
SCK
0
2
3
4
5
6
7
1
8
3
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