參數(shù)資料
型號: 25AA256T-EST
廠商: Microchip Technology Inc.
英文描述: DBL BNDPOST MTG BASE 10/PKG (BLACK) RoHS Compliant: Yes
中文描述: 256K SPI總線串行EEPROM
文件頁數(shù): 2/26頁
文件大?。?/td> 367K
代理商: 25AA256T-EST
25AA256/25LC256
DS21822C-page 10
Preliminary
2003 Microchip Technology Inc.
2.5
Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
The Write-In-Process (WIP) bit indicates whether the
25XX256 is busy with a write operation. When set to a
1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the Status register. These commands are shown in
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
7
654
3
2
1
0
W/R
–––
W/R
R
WPEN
X
BP1
BP0
WEL
WIP
W/R = writable/readable. R = read-only.
SO
SI
CS
9
1011
12131415
11
0
00
76
5
4
2
1
0
instruction
data from Status register
high-impedance
SCK
0
2
34
56
7
1
8
3
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25AA256T-I/SN 功能描述:電可擦除可編程只讀存儲器 32kx8 - 1.8V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
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