參數(shù)資料
型號: 25LC256T-EMFG
廠商: Microchip Technology Inc.
元件分類: EEPROM
英文描述: 256K SPI Bus Serial EEPROM
中文描述: 256K SPI總線串行EEPROM
文件頁數(shù): 10/26頁
文件大小: 367K
代理商: 25LC256T-EMFG
25AA256/25LC256
DS21822C-page 10
Preliminary
2003 Microchip Technology Inc.
2.5
Read Status Register Instruction
(
RDSR
)
The Read Status Register instruction (
RDSR
) provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
The
Write-In-Process (WIP)
bit indicates whether the
25XX256 is busy with a write operation. When set to a
1
’, a write is in progress, when set to a ‘
0
’, no write is
in progress. This bit is read-only.
The
Write Enable Latch (WEL)
bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
1
’, the latch allows writes to the array, when set to a
0
’, the latch prohibits writes to the array. The state of
this bit can always be updated via the
WREN
or
WRDI
commands regardless of the state of write protection
on the Status register. These commands are shown in
Figure 2-4 and Figure 2-5.
The
Block Protection (BP0 and BP1)
bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the
WRSR
instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the
RDSR
timing sequence.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (
RDSR
)
7
6
X
5
X
4
X
3
2
1
R
0
R
W/R
WPEN
W/R = writable/readable. R = read-only.
W/R
BP1
W/R
BP0
WEL
WIP
SO
SI
CS
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
7
6
5
4
2
1
0
instruction
data from Status register
high-impedance
SCK
0
2
3
4
5
6
7
1
8
3
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