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參數(shù)資料
| 型號： | 25LC256T-IST |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | LED 470NM ROUND BLUE 3MM |
| 中文描述： | 256K SPI總線串行EEPROM |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 367K |
| 代理商： | 25LC256T-IST |
25AA256/25LC256
DS21822C-page 6
Preliminary
2003 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25XX256 is a 32768 byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller
families,
PICmicro
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol.
The 25XX256 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX256 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
including
Microchip’s
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25XX256 followed by
the 16-bit address, with the first MSB of the address
being a don’t care bit. After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (7FFFh), the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 2-1).
2.3
Write Sequence
Prior to any attempt to write data to the 25XX256, the
write enable latch must be set by issuing the
WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX256. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the
WREN
instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a
WRITE
instruction, followed by the 16-bit address, with the first
MSB of the address being a don’t care bit, and then the
data to be written. Up to 64 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the
n
th
data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless
of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size - 1. If a Page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
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| 25LC256-EMF | 256K SPI Bus Serial EEPROM |
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| 25LC256-EP | 256K SPI Bus Serial EEPROM |
| 25LC256-ISTG | GT 8C 8#16 SKT PLUG |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 25LC256T-ISTG | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K SPI Bus Serial EEPROM |
| 25LC256X-E/ST | 功能描述:電可擦除可編程只讀存儲器 256k 32KX8 2.5V SER EE EXT RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 25LC256XEMF | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K SPI Bus Serial EEPROM |
| 25LC256XEP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K SPI Bus Serial EEPROM |
| 25LC256XESM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K SPI Bus Serial EEPROM |
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