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參數(shù)資料
| 型號(hào)： | 27384A |
| 英文描述： | ±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry |
| 中文描述： | 增加關(guān)于Am29BDD160G時(shí)鐘速度和更快的初步突發(fā)存取 |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | 27384A |
4
Increased Clock Speeds and Faster Initial Burst Access
December 12, 2002
SUMMARY OF SILICON REVISION 4 AND
4A DIFFERENCES
Hardware/Physical Considerations
Burst Initial Access Delay Control
Revision 4 and 4a differ by one clock cycle for a partic-
ular setting. See burst initial delay access discussion
above for details.
CFI Device Geometry Definition, Number if Erase
Block Regions, memory location 2Ch while in x32
mode)
Revision 4 has a value of 4h while Revision 4a has a
value of 3h.
Software Considerations
CFI Device Geometry Definition
The CFI Device Geometry Definition change between
revisions provides software/firmware to determine of
the revision level of a given Flash device by interrogat-
ing the CFI information. Software/firmware can then
program the device appropriately for proper operation
by programming the Burst Initial Access Delay. This
assumes that the Flash device has a speed rating (D,
C, or A) compatible with the microprocessor.
Datasheet/Part Number Considerations
Device Speed and Clock Rate Information
The Product Selector Guide and Ordering Information
sections in the Datasheet have details on device speed
and clock rate.
Revisions 4 and earlier have options for 80C and 90A
while Revision 4a has options for 54D, 64C, and 65A.
The 80C and 90A options for Revisions 4 are obsolete
with Revision 4a.
Ordering information (Part Number)
Revisions 4 and earlier have the following valid combi-
nations, which are obsolete with Revision 4a:
Am29BDD160GX80CYZ, Am29BDD160GX90AYZ,
and AM29BDD160GB-DS3/4/5/6/7
Revision 4a has the following valid combinations:
Am29BDD160GX54DYZ, Am29BDD160GX64CYZ,
Am29BDD160GX65AYZ,and Am29BDD160GY65DYZ
Note:
X, Y, and Z reflect user selectable options, i.e. X = Boot Sec-
tor, Y = Package, Z = Temperature
Additional Considerations
It is important that each user understand that the micro-
processor of choice must be paired to a Flash device
with a compatible speed and clock rate. Achieving in-
tended operation of the system is not just a matter of
interrogating the CFI Device Geometry Definition to de-
termine the revision level and configuring the Flash
device. For example:
A Flash Device must meet or exceed the microproces-
sor clock speed. Assume that a Revision 4 (or earlier
revision) Flash device with a Device Speed and Clock
Rate of 80C (80 ns, 56 MHz) is used. Then later, when
a revision 4a device replaces the Revision 4 device, a
Flash Device Speed and Clock Rate 65A (65 ns, 40
MHz) cannot be used. The reason is the 65A part has
a maximum clock rate of 40 MHz, which is less than the
80C Revision 4 device.
The example above demonstrates that simply interro-
gating the CFI Device Geometry Definition to
determine the revision level is not sufficient. There is
no way to determine that an A (40 MHz) device is in a
system clocked at a C speed (56 MHz). The device
must be capable of operating properly at the micropro-
cessor clock speed.
Trademarks
Copyright 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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