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參數(shù)資料
| 型號： | 27C010 |
| 廠商： | Atmel Corp. |
| 英文描述： | 1 Megabit 128K x 8 OTP CMOS EPROM |
| 中文描述： | 1兆位128K的× 8檢察官辦公室的CMOS存儲器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 256K |
| 代理商： | 27C010 |
AC Programming Characteristics
T
A
= 25
±
5°C, V
CC
= 6.5
±
0.25 V, V
PP
= 13.0
±
0.25V
Sym-
bol
Parameter
Test
Conditions*
(1)
Limits
Min
Units
Max
t
AS
t
CES
t
OES
t
DS
t
AH
t
DH
Address Setup Time
2
μ
s
CE Setup Time
2
μ
s
OE Setup Time
2
μ
s
Data Setup Time
2
μ
s
Address Hold Time
0
μ
s
Data Hold Time
OE High to Output
Float Delay
(2)
V
PP
Setup Time
2
μ
s
t
DFP
0
130
ns
t
VPS
t
VCS
t
PW
t
OE
2
μ
s
V
CC
Setup Time
PGM Program Pulse Width
(3)
2
μ
s
95
105
μ
s
Data Valid from OE
V
PP
Pulse Rise TIme During
Programming
150
ns
t
PRT
50
ns
*AC Conditions of Test:
Input Rise and Fall Times (10% to 90%)..........20 ns
Input Pulse Levels...............................0.45V to 2.4V
Input Timing Reference Level...............0.8V to 2.0V
Output Timing Reference Level............0.8V to 2.0V
Notes: 1. V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
2. This parameter is only sampled and is not 100%
tested. Output Float is defined as the point where
data is no longer driven — see timing diagram.
3. Program Pulse width tolerance is 100
μ
sec
±
5%.
Atmel’s 27C010/L Integrated
Product Identification Code
Codes
Pins
Hex
Data
A0
O7 O6 O5 O4 O3 O2 O1 O0
Manufacturer
Device Type
0
1
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
1E
05
Rapid
Programming Algorithm
A 100
μ
s PGM pulse width is used to program. The ad-
dress is set to the first location. V
CC
is raised to 6.5V and
V
PP
is raised to 13.0V. Each address is first programmed
with one 100
μ
s PGM pulse without verification. Then a
verification / reprogramming loop is executed for each ad-
dress. In the event a byte fails to pass verification, up to
10 successive 100
μ
s pulses are applied with a verifica-
tion after each pulse. If the byte fails to verify after 10
pulses have been applied, the part is considered failed.
After the byte verifies properly, the next address is se-
lected until all have been checked. V
PP
is then lowered to
5.0V and V
CC
to 5.0V. All bytes are read again and com-
pared with the original data to determine if the device
passes or fails.
AT27C010/L
3-159
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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