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參數資料
| 型號： | 27C1024-12 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 1M-BIT [128K x 8/64K x 16] CMOS EPROM |
| 中文描述： | 100萬位[128K的x 8/64K × 16]的CMOS存儲器 |
| 文件頁數： | 4/19頁 |
| 文件大?。?/td> | 795K |
| 代理商： | 27C1024-12 |
4
REV. 4.6, JAN. 14, 2003
P/N: PM0156
MX27C1100/27C1024
VIL(for MX27C1024), OE at VIL, CE at VIH(for
MX27C1100)and VPP at its programming voltage.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25
°
C
±
5
°
C ambient
temperature range that is required when programming
the MX27C1100/1024.
To activate this mode, the programming equipment
must force 12.0
±
0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C1100/1024, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.
READ MODE
The MX27C1100/1024 has two control functions, both
of which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and
addresses have been stable for at least tACC - t OE.
WORD-WIDE MODE
With BYTE/VPP at VCC
±
0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C1100/1024
When the MX27C1100/1024 is delivered, or it is
erased, the chip has all 1M bits in the "ONE" or HIGH
state. "ZEROs" are loaded into the MX27C1100/1024
through the procedure of programming.
For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.
VCC must be applied simultaneously or before VPP, and
removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm
is shown in Figure 1). The programming is achieved by
applying a single TTL low level 100us pulse to the PGM
input after addresses and data line are stable. If the data
is not verified, an additional pulse is applied for a
maximum of 25 pulses. This process is repeated while
sequencing through each address of the device. When
the programming mode is completed, the data in all
address is verified at VCC = VPP = 5V
±
10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27C1100/1024's in parallel
with different data is also easily accomplished by using
the Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C1100/1024 may be
common. A TTL low-level program pulse applied to an
MX27C1100/1024 CE input with VPP = 12.5
0.5 V will
program the MX27C1100/1024. A high-level CE input
inhibits the other MX27C1100/1024s from being
programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE and CE at
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