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參數(shù)資料
| 型號(hào)： | 27C16Q883 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 16,384-Bit (2048 x 8) UV Erasable CMOS PROM Military Qualified |
| 中文描述： | 16,384位（2048 × 8）紫外線擦除的CMOS PROM的軍用合格 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 111K |
| 代理商： | 27C16Q883 |
Programming Waveforms
V
PP
e
25V
g
11V, V
CC
e
5V
g
5% (Note 3)
TL/D/10329–4
Note:
All times shown in parentheses are minimum and in
m
s unless otherwise specified.
Note 1:
National’s standard product warranty applies only to devices programmed to specifications described herein.
Note 2:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The 27C16 must not be inserted into or removed from a board
with V
PP
at 25V
g
1V to prevent damage to the device.
Note 3:
The maximum allowable voltage which may be applied to the V
PP
pin during programming is 26V. Care must be taken when switching the V
PP
supply to
prevent overshoot exceeding this 26V maximum specification. A 0.1
m
F capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Functional Description
DEVICE OPERATION
The six modes of operation of the 27C16 are listed in Table
I. It should be noted that all inputs for the six modes are at
TTL levels. The power supplies required are a 5V V
CC
and a
V
PP
. The V
PP
power supply must be at 25V during the three
programming modes, and must be at 5V in the other three
modes.
Read Mode
The 27C16 has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip
Enable (CE) is the power control and should be used for
device selection. Output Enable (OE) is the output control
and should be used to gate data to the output pins, indepen-
dent of device selection. Assuming that addresses are sta-
ble, address access time (t
ACC
) is equal to the delay from
CE to output (t
CE
). Data is available at the outputs t
OE
after
the falling edge of OE, assuming that CE has been low and
addresses have been stable for at least t
ACC
–t
OE
. The
27C16 requires one address transition after initial power-up
to reset the outputs.
Standby Mode
The 27C16 has a standby mode which reduces the active
power dissipation by 98%, from 26.25 mW to 0.53 mW. The
27C16 is placed in the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the outputs
are in a high impedance state, independent of the OE input.
Output OR-Tying
Because 27C16s are usually used in larger memory arrays,
National has provided a 2-line control function that accom-
modates this use of multiple memory connections. The
2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that CE (pin 18) be decoded and used as the pri-
mary device selecting function, while OE (pin 20) be made a
common connection to all devices in the array and connect-
ed to the READ line from the system control bus. This as-
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 26.5V on pin 21 (V
PP
) will damage the
27C16.
Initially, and after each erasure, all bits of the 27C16 are in
the ‘‘1’’ state. Data is introduced by selectively program-
ming ‘‘0s’’ into the desired bit locations. Although only ‘‘0s’’
will be programmed, both ‘‘1s’’ and ‘‘0s’’ can be presented
in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is
by ultraviolet light erasure.
The 27C16 is in the programming mode when the V
PP
pow-
er supply is at 25V and OE is at V
IH
. It is required that a
0.1
m
F capacitor be placed across V
PP
, V
CC
to ground to
suppress spurious voltage transients which may damage
the device. The data to be programmed is applied 8 bits in
parallel to the data output pins. The levels required for the
address and data inputs are TTL.
When the address and data are stable, a 50 ms, active high,
TTL program pulse is applied to the CE/PGM input. A pro-
gram pulse must be applied at each address location to be
programmed. You can program any location at any timeD
either individually, sequentially, or at random. The program
pulse has a maximum width of 55 ms. The 27C16 must not
be programmed with a DC signal applied to the CE/PGM
input.
6
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