參數(shù)資料
型號: 27C2001
廠商: 意法半導體
英文描述: 2 Mbit 256Kb x 8 UV EPROM and OTP EPROM
中文描述: 2兆位的256Kb × 8紫外線存儲器和OTP存儲器
文件頁數(shù): 4/17頁
文件大小: 114K
代理商: 27C2001
M27C2001
4/17
DEVICE OPERATION
The operating modes of the M27C2001 are listed
in theOperating Modes table. A single powersup-
ply isrequired in the read mode. All inputs are TTL
levels except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27C2001 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Datais available atthe output aftera delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C2001 hasa standby mode which reduc-
es the supply current from 30mA to 100
μ
A. The
M27C2001 is placed in the standby mode by ap-
plying a CMOS high signalto the E input. When in
the standbymode, theoutputs are in a high imped-
ance state, independent of the G input.
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 4. AC Testing Load Circuit
AI01823B
1.3V
OUT
CL
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 6. Capacitance
(1)
(T
A
= 25
°
C, f = 1 MHz)
Symbol
Note: 1. Sampled only, not 100% tested.
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
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