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參數(shù)資料
| 型號： | 27C512-10 |
| 廠商： | Macronix International Co., Ltd. |
| 英文描述： | 512K-BIT [64Kx8] CMOS EPROM |
| 中文描述： | 為512k位[64Kx8]的CMOS存儲器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 772K |
| 代理商： | 27C512-10 |
2
P/N:PM0235
REV. 4.8, AUG. 26, 2003
MX27C512
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25
°
C
±
5
°
C ambient
temperature range that is required when programming
the MX27C512.
To activate this mode, the programming equipment
must force 12.0
±
0.5(VH) on address line A9 of the
device. Two identifier bytes may then be sequenced
from the device outputs by toggling address line A0 from
VIL to VIH. All other address lines must be held at VIL
during auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C512, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB (Q7)
defined as the parity bit.
READ MODE
The MX27C512 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX27C512 has a CMOS standby mode which
reduces the maximum VCC current to 100uA . It is
placed in CMOS standby when CE is at VCC
±
0.3 V.
The MX27C512 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C512
When the MX27C512 is delivered, or it is erased, the
chip has all 512K bits in the "ONE" or HIGH state.
"ZEROs" are loaded into the MX27C512 through the
procedure of programming.
For programming, the data to be programmed is applied
with 8 bits in parallel to the data pins.
Vcc must be applied simultaneously or before Vpp, and
removed simultaneously or after Vpp. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across Vpp and ground to suppress spurious
voltage transients which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when
the programming voltage OE/VPP = 12.75V is applied,
with VCC = 6.25 V, (Algorithm is shown in Figure 1). The
programming is achieved by applying a single TTL low
level 100us pulse to the CE input after addresses and
data line are stable. If the data is not verified, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through
each address of the device. When the programming
mode is completed, the data in all address is verified at
VCC = 5V
±
10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27C512s in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C512 may be common. A
TTL low-level program pulse applied to an MX27C512
CE input with OE/VPP = 12.5
±
0.5V will program that
MX27C512. A high-level CE input inhibits the other
MX27C512s from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE/VPP and
CE, at VIL. Data should be verified tDV after the falling
edge of CE.
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