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參數(shù)資料
| 型號(hào)： | 27C512A-90SO |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 512K (64K x 8) CMOS EPROM |
| 中文描述： | 為512k（64K的× 8）的CMOS存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | 27C512A-90SO |
1996 Microchip Technology Inc.
DS11173E-page 5
27C512A
FIGURE 1-2:
PROGRAMMING WAVEFORMS (1)
TABLE 1-6:
MODES
Operation Mode
CE
OE/V
PP
A9
O0 - O7
Read
V
IL
V
IL
X
D
OUT
Program
V
IL
V
H
X
D
IN
Program Verify
V
IL
V
IL
X
D
OUT
Program Inhibit
V
IH
V
H
X
High Z
Standby
V
IH
X
X
High Z
Output Disable
V
IL
V
IH
X
High Z
Identity
V
IL
V
IL
V
H
Identity Code
X = Don’t Care
t
OPW
t
OEH
t
CE
(2)
V
IH
V
IL
V
IH
V
IL
6.5 V (3)
5.0V
V
IH
V
IL
Address
Data
V
CC
CE
Address Stable
t
DS
t
AS
Data In Stable
Data Out Valid
Verify
t
VCS
Notes:
The input timing reference level is 0.8V for V
IL
and 2.0V for V
IH
.
t
DF
and t
OE
are characteristics of the device but must be accommodated by the programmer.
V
CC
= 6.5V
±
0.25V, V
PP
= V
H
= 13.0V
±
0.5V for express programming algorithm.
(1)
(2)
(3)
t
DH
t
OR
t
DF
(2)
t
AH
t
PRT
t
CES
t
PW
t
OES
13.0 V (3)
V
IL
OE/V
PP
Program
1.2
Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
a)
the CE pin is low to power up (enable) the chip
b)
the OE/V
PP
pin is low to gate the data to the
output pins
For Read operations, if the addresses are stable, the
address access time (t
ACC
) is equal to the delay from
CE to output (t
CE
). Data is transferred to the output
after a delay (t
OE
) from the falling edge of OE/V
PP
.
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