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參數(shù)資料
| 型號： | 27LC128-25SO |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 128K (16K x 8) CMOS EPROM |
| 中文描述： | 128K的（16K的× 8）的CMOS存儲器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 62K |
| 代理商： | 27LC128-25SO |
1996 Microchip Technology Inc.
DS11003K-page 5
27C128
FIGURE 1-2:
PROGRAMMING WAVEFORMS (1)
TABLE 1-6:
MODES
Operation Mode
CE
OE
PGM
V
PP
A9
O0 - O7
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IL
X
X
V
IH
V
IL
V
IH
V
IL
V
IH
X
X
V
IH
V
IH
V
CC
V
H
V
H
V
H
V
CC
V
CC
V
CC
X
X
X
X
X
X
V
H
D
OUT
D
IN
D
OUT
High Z
High Z
High Z
Identity Code
X = Don’t Care
V
IH
V
IL
V
IH
V
IL
13.0 V (3)
5.0 V
6.5 V (3)
5.0 V
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Address
Data
V
PP
V
CC
CE
PGM
OE
Address Stable
t
AH
t
DS
t
DH
t
VPS
t
DF
(2)
t
AS
Program
Data In Stable
Data Out Valid
Verify
t
VCS
The input timing reference is 0.8V for V
IL
and 2.0V for V
IH
.
t
DF
and t
OE
are characteristics of the device but must be accommodated by the programmer.
Vcc = 6.5V
±
0.25V, V
PP
= V
H
= 13.0V
±
0.25V for Express algorithm.
Notes:
(1)
(2)
(3)
t
PW
t
OPW
t
OES
t
OE
(2)
t
CES
High Z
1.2
Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
a)
the CE pin is low to power up (enable) the chip
b)
the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (t
ACC
) is equal to the delay from
CE to output (t
CE
). Data is transferred to the output
after a delay from the falling edge of OE (t
OE
).
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