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參數(shù)資料
| 型號： | 2844B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS |
| 中文描述： | 高性能的電流模式PWM控制器 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大小： | 336K |
| 代理商： | 2844B |
www.ti.com
Shutdown Technique
The PWM controller (see
Figure 5
) can be shut down by two methods: either raise the voltage at I
SENSE
above
1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output
of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output
remains low until the next clock cycle after the shutdown condition at the COMP or I
SENSE
terminal is removed.
In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling
V
CC
below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset.
330
1 k
500
To Current-Sense
Resistor
Shutdown
Shutdown
COMP
V
REF
I
SENSE
R
T
0.1
μ
F
C
T
R1
R2
I
SENSE
R
SENSE
C
V
REF
R
T
/C
T
I
SENSE
TL284xB, TL384xB
HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS
SLVS610A–AUGUST 2006–REVISED SEPTEMBER 2006
APPLICATION INFORMATION (continued)
Figure 5. Shutdown Techniques
A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see
Figure 6
). Note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
Figure 6. Slope Compensation
13
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