參數(shù)資料
型號(hào)： 28F004S3
廠商： Intel Corp.
英文描述： BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
中文描述： 字節(jié)寬的SMART 3 FlashFile Memory系列4，8和16兆比特
文件頁(yè)數(shù)： 17/41頁(yè)
文件大?。?/td> 703K
代理商： 28F004S3
E
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY
17
PRELIMINARY
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to
“1.” Also,
reliable block erasure can only occur when
V
CC
= V
CC2
and V
PP
= V
PPH1/2
. In the absence of
this high voltage, block contents are protected
against erasure. If block erase is attempted while
V
≤
V
PPLK
, SR.3 and SR.5 will be set to “1.”
Successful
block
erase
corresponding block lock-bit be cleared or, if set,
that RP# = V
HH
. If block erase is attempted when
the corresponding block lock-bit is set and
RP# = V
IH
, the block erase will fail, and SR.1 and
SR.5 will be set to “1.” Block erase operations with
V
IH
< RP# < V
HH
produce spurious results and
should not be attempted.
requires
that
the
4.6
Program Command
Program is executed by a two-cycle command
sequence. Program setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the program and verify algorithms
internally. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 8). The CPU can detect
the completion of the program event by analyzing
the RY/BY# pin or status register bit SR.7.
When program is complete, status register bit SR.4
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in
read status register mode until it receives another
command.
Reliable program only occurs when V
CC
= V
CC2
and
V
= V
. In the absence of this high voltage,
memory contents are protected against program
operations. If a program operation is attempted
while V
PP
≤
V
PPLK
, the operation will fail, and status
register bits SR.3 and SR.5 will be set to “1.”
A successful program operation also requires that
the corresponding block lock-bit be cleared or, if
set, that RP# = V
HH
. If a program operation is
attempted when the corresponding block lock-bit is
set and RP# = V
IH
, the operation will fail, and SR.1
and SR.4 will be set to “1.” Program operations with
V
IH
< RP# < V
HH
produce spurious results and
should not be attempted.
4.7
Block Erase Suspend
Command
The Block Erase Suspend command allows
block-erase interruption to read or program data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to
“1”).
RY/BY#
will
also
Specification t
WHRH2
defines the block erase
suspend latency.
transition
to
V
.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can also be suspended. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the RY/BY# output will
transition to V
OL
. However, SR.6 will remain “1” to
indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V
OL
. After the Erase
Resume
command
is
automatically outputs status register data when
read (see Figure 9). V
PP
must remain at V
PPH1/2
(the same V
PP
level used for block erase) while
block erase is suspended. RP# must also remain at
V
IH
or V
HH
(the same RP# level used for block
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
written,
the
device
相關(guān)PDF資料
PDF描述
28F004S5 BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
28F004SC BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
28F008B3 SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
28F008C3 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
28F008SA 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F004S5 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
28F004SC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
28F008B3 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE
28F008BE-T/B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F008BV-T/B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Boot Flash
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